专利摘要:
A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406). The semiconductor chip (105′) is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105′) is hot-pressed by means of a heating head (106) for bonding on the substrate (102). In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
公开号:US20010000079A1
申请号:US09/729,191
申请日:2000-12-05
公开日:2001-03-29
发明作者:Mitsuo Usami;Kunihiro Tsubosaki;Kunihiko Nishi
申请人:Mitsuo Usami;Kunihiro Tsubosaki;Kunihiko Nishi;
IPC主号:H01L21-6835
专利说明:
[1] 1. This application is a Continuation application of Ser. No. 08/952,344, filed Nov. 18, 1997, the contents of which are incorporated herein by reference in their entirety, which is an application under 35 USC 371 of PCT/JP96/01263, filed May 14, 1996. FIELD OF THE INVENTION
[2] 2. This invention relates to a semiconductor device and also to a method for making the same. More particularly, the invention relates to a semiconductor device which is very thin, is unlikely to break by bending stress, and is suitable for use as various types of cards, and also to a method for making such a thin semiconductor device stably and at low costs. BACKGROUND ART
[3] 3. The formation of various types of cards such as IC cards has been proposed by utilizing a very thin semiconductor device. Hitherto, it has been difficult to obtain such cards which can stand use in practical applications owing to the is ease in breakage by bending stress.
[4] 4. Conventional assembling technologies of thin semiconductor devices are described, for example, in “LSI Handbook” (edited by the Electronic Communication Society and published by Ohom Corporation on Nov. 30, 1984, pp. 406-416). In these conventional semiconductor device assembling technologies, there have been employed semiconductor wafers which have such a thickness of approximately 200 μm or over that they are very unlikely to break when direct handling is done.
[5] 5. As is well known in the art, a polishing method has been in wide use for thinning a semiconductor wafer. In order to uniformly process a semiconductor wafer, for example, with a process accuracy of 5% according to the polishing method, it is essential that the semiconductor wafer be set parallel to a polishing device at high accuracy and high reproducibility. For realizing such a very high level of parallel setting, a very expensive apparatus is necessary, thus having involved a difficulty in practical applications.
[6] 6. An attempt has been made to effect a polishing method while monitoring the thickness of a semiconductor wafer. If a region with a large area is polished according to this method, it takes a very long time, resulting in the lowering of productivity.
[7] 7. Alternatively, when a semiconductor wafer is polished to a very small thickness, for example, of approximately 0.1 μm, there arises the problem that various types of semiconductor devices, such as transistors, formed on the surface of the semiconductor wafer are broken owing to the stress caused by the polishing.
[8] 8. Moreover, when such a thinned semiconductor chip is directly handled according to the prior art technologies, a problem is involved in that the semiconductor chip is broken. Thus, it has been difficult to form a semiconductor device in high yield at low costs. DISCLOSURE OF THE INVENTION
[9] 9. Accordingly, an object of the invention is to provide a semiconductor device which can solve the problems of the prior art technologies, is unlikely to break owing to the bending stress exerted thereon, and can be utilized as various types of cards.
[10] 10. Another object of the invention is to provide a method for making a semiconductor device which is able to thin a semiconductor chip to a level of approximately 0.1 to 110 μm and wherein such a very thin chip can be handled without involving any cracking occasion.
[11] 11. In order to achieve the above objects, there is provided a semiconductor device which comprises a thin semiconductor chip and a substrate which are faced to each other via an organic adhesive layer containing a multitude of conductive particles therein, a pad made of a conductive film and formed on the surface at the substrate side of the semiconductor chip, and a substrate electrode provided on the surface at the chip side of the substrate such that the pad and the substrate electrode are electrically connected to each other via the conductive particles.
[12] 12. The thin semiconductor chip and the substrate made of an elastic material, which are arranged in face-to-face relation with each other, are bonded and fixed together through the organic adhesive layer, so that when exerted with a bending stress from outside, they are very unlikely to break.
[13] 13. The electric connection between the semiconductor chip and the substrate is ensured by means of the conductive particles present in the organic adhesive. The conductive particles are deformed by application of a pressure to the pad of the semiconductor chip and the electrode of the substrate which are arranged in face-to-face relation with each other. The thus deformed conductive particles serve to electrically connect the semiconductor chip and the substrate with each other, and thus, the electric connection between the pad and the electrode is very reliable.
[14] 14. A passivation film having a given pattern is formed on the semiconductor chip, and the pad is formed on a portion where no passivation film has been formed. The thickness of the pad is smaller than that of the passivation film, so that the conductive particles present between the pad and the electrode being faced to each other are effectively suppressed from migration to outside. In this way, the pad and the electrode can be reliably, electrically connected by means of the conductive particles.
[15] 15. A method for making a semiconductor device for the purpose of achieving the another object of the invention comprises bringing a semiconductor wafer, which has been attached to a tape, into contact with an etchant while rotating the wafer within an in-plane direction thereof or laterally reciprocating the wafer at a high speed so that the semiconductor wafer is uniformly reduced in thickness by etching, dicing the thus reduced semiconductor wafer for division into a plurality of chips, and subjecting individual thin chips to hot-pressing against a substrate to bond them on the substrate one by one.
[16] 16. While rotating the wafer in an in-plane direction thereof or laterally reciprocating it at a high speed, the semiconductor wafer is brought into contact with an etchant, so that the wafer is very uniformly etched. Thus, there can be obtained a very thin semiconductor wafer (0.1 to 110 μm) which is substantially free of any irregularities and distortion.
[17] 17. A plurality of the thin semiconductor chips which are obtained by dividing the very thin semiconductor wafer into smaller-sized chips are, respectively, separated from the tape which is a first substrate, and are heated on a second substrate and welded by compression pressure. Thus, irrespective of the semiconductor chips being very thin, the chips can be fixedly adhered or bonded on the second substrate without involving any undesirable cracking occasion. Especially, when a non-rigid tape is used as the first substrate, only a desired chip is pushed upwardly and is selectively heated, so that it is very easy to adhere the desired chip on the second substrate. For the division of the wafer into the chips, it is preferred from the standpoint of practical applications that the wafer is completely separated into individual chips by dicing.
[18] 18. The adhesion between the second substrate and the semiconductor chip is effected through a conductive adhesive, by which any wire bonding becomes unnecessary, thus being very effective in the simplification of the steps and the reduction of costs. BRIEF ILLUSTRATION OF THE DRAWINGS
[19] 19.FIG. 1 is a view illustrating a first embodiment of the invention;
[20] 20.FIG. 2 is a view illustrating a prior art method;
[21] 21.FIG. 3 is a plan view illustrating an embodiment of the invention;
[22] 22.FIG. 4(1) is a plan view showing the connection between a chip and a substrate;
[23] 23.FIG. 4(2) is a sectional view showing the connection between the chip and the substrate;
[24] 24.FIG. 4(3) is a sectional view showing a connection portion between the chip and the substrate;
[25] 25. FIGS. 5(1) to 5(3) are, respectively, schematic views illustrating the steps of a second embodiment of the invention;
[26] 26. FIGS. 6(1) to 6(5) are, respectively, schematic views illustrating the steps of a third embodiment of the invention; and
[27] 27. FIGS. 7(1) to 7(6) are, respectively, schematic views illustrating the steps of a fourth embodiment of the invention. BEST MODE FOR CARRYING OUT THE INVENTION EXAMPLE 1
[28] 28. As shown in FIG. 1, a thin semiconductor wafer 105 is placed on a tape 107 (HA-1506 of Hitachi Chemical Ltd.) held with a frame 101. This semiconductor wafer 105 is completely cut off by means of dicing grooves 104 and separated into a plurality of chips 105′.
[29] 29. The separated chips 105′ are pushed upwardly from the back side of the tape 107 by means of a heating head 106, and is urged against a substrate 102 on which an adhesive 103 has been preliminarily applied, thereby causing the chip to be thermally bonded to the substrate 102. The adhesive 103 is an anisotropic conductive adhesive made of a compound material of an organic material and conductive particles, so that an electrode (not shown) formed on the substrate 102 and an electrode (i.e. a pad, not shown) of the thin chip 105 are electrically connected with each other through the conductive particles contained in the adhesive 103 by application of a compression pressure and heat.
[30] 30. It will be noted that the chip 105′ is so thin as approximately 0.1 to 110 μm in thickness and is bendable. If the thickness is smaller than 0.1 μm, a difficulty is involved in the formation of various types of semiconductor devices on the chip 105′. If the thickness is larger than 110 μm, cracking may occur on bending of the chip. The thickness of the chip 105′ should be preferably within a range of 0.1 to 110 μM.
[31] 31. The tape 107 is non-rigid in nature. When the tape 107 is pushed upwardly while heating the tape 107 with the heating head 106, the thin chip 105′ on the tape 107 is also pushed upwardly, thereby ensuring uniform and stable bonding with the substrate 102 placed above.
[32] 32.FIG. 3 is a view showing a plane structure of FIG. 1 wherein the tape 107 is held with a ring-shaped frame 101 and the wafer 105 is separated into a plurality of the chips 105′ by the dicing grooves 104. A periphery 304 of the wafer 105 is within the inner side of the frame 101 and is adhered to the tape 107 as flattened. The frame 101 is formed of a stainless steel or a plastic material. Although the wafer 105 is very thin as having a thickness of from 0.1 to 110 μm, it is strongly adhered to the tape 107 by means of a pressure sensitive adhesive. In this condition, when the wafer 105 is diced under conditions where it is adhered to the tape 107, the resultant thin chips 105′ do not individually peel off from the tape 107.
[33] 33.FIG. 4 shows the state observed after the thin chip 105′ has been bonded to the substrate 102. FIG. 4(1) is a plan view and FIG. 4(2) is a sectional view. The thin chip 105′ is bonded to a given position of the substrate 102. An electrode (pad) formed on the thin chip 105′ and an electrode (substrate electrode) formed on the substrate 102 are mutually connected through face down bonding. Alternatively, they may be mutually connected with wire bonding or a conductive paste.
[34] 34. The mounting of the thin chips may be simply, easily realized as set out above, so that the thinning of, the impartment of high functionality to and low costs of semiconductor devices can be facilitated, thus enabling one to extend the ranges of application in many and new fields.
[35] 35. It will be noted that FIG. 4(3) is an enlarged, schematic sectional view showing a portion of connection between the thin chip 105′ and the substrate 102 shown in FIG. 4(1) and 4(2). As shown in FIG. 4(3), the pad (i.e. an electrode provided on the semiconductor chip) 405 made of a conductive film is formed on a surface portion of the thin chip 105′ which is free of any passivation film 108, and is connected with the substrate electrode 412 formed on the surface of the substrate 102 by means of the conductive particles 406. An organic film (an organic adhesive film) 409 is provided between the substrate 102 and the chip 105′. The conductive particles 410 are contained in the organic film 409 and ensures electric conduction between the pad 405 and the substrate electrode 412 therewith. In this case, as shown in FIG. 4(3), the thickness of the passivation film 108 is larger than that of the pad 405. This effectively suppresses the migration, to outside, of the conductive particles 406 intervening between the pad 405 and the substrate electrode 412. As a consequence, the pad 405 and the substrate electrode 412 are very reliably, electrically connected with each other.
[36] 36. In a prior art method, as shown in FIG. 2, a chip 202 placed on a tape 203 is handled with a vacuum chuck 201 and moved on other substrate (not shown). More particularly, the chip 202 placed on the tape 203 is one which is individually formed by dicing of a wafer. The chips 202 stuck up with a stick-up pin 204 are sucked by means of the vacuum chuck 201 and moved one by one.
[37] 37. The tape 203 is applied with a pressure sensitive adhesive, which lowers in adhesion properties by irradiation of Ultraviolet (UV) light or by application of heat, but slight adhesiveness is still left. Accordingly, the chip 202 can be separated from the tape 203 by means of the stick-up pin 204 operated in synchronism with the vacuum chuck 201.
[38] 38. However, in the known method of sticking up the chip with the stick-up pin 204, when the chip 202 is very thin with its thickness being 0.1 to 110 μm, the chip 202 is apt to crack. Thus, productivity lowers, making it difficult to widely use the method in practical applications. EXAMPLE 2
[39] 39. This example illustrates a method of thinning a semiconductor wafer.
[40] 40. As shown in FIG. 5(1), a Si wafer 105 is fixed, by means of a pressure sensitive adhesive, on a tape 107 attached to a frame 101, after which while the Si wafer 105 is rotated at a high speed of 1,000 r.p.m. or over, an etchant 502 is dropped from an etching nozzle 501 on the Si wafer 105, thereby etching the surface of the Si wafer 105. The etchant 502 used in this example consists of an aqueous solution of potassium hydroxide (concentration: 40%). Etchants other than that of potassium hydroxide may also be used.
[41] 41. Since the etchant 502 is dropped while rotating the Si wafer 105 at a high speed, the etchant 502 dropped on the surface of the Si wafer 105 moves laterally relative to the surface of the Si wafer 105 at a high speed as shown in FIG. 5(2). This causes the surface of the Si wafer 105 to be uniformly etched, enabling one to make the Si wafer 105 thin without involving any difference in level or any damage.
[42] 42. As shown in FIG. 5(3), when the etchant 502 is dropped while reciprocating at a high speed of 1,000 r.p.m. or over, the etchant 502 likewise moves at a high speed laterally along the surface of the Si wafer 105. Thus, the surface of the Si wafer 105 is uniformly etched without producing any difference in level or any damage, and can thus be thinned. EXAMPLE 3
[43] 43.FIG. 6 is a process chart showing a further embodiment of the invention.
[44] 44. As shown in FIG. 6(1), a Si wafer 105 is fixed on a tape 107 attached to a frame 101, after which the Si wafer 105 is etched and thinned according to the method illustrated in Example 2, thereby forming a sectional structure shown in FIG. 6(2). Further, as shown in FIG. 6(3), the Si wafer 105 is formed with dicing grooves 104 to divide the Si wafer 105 into a plurality of chips 105′.
[45] 45. Then, as shown in FIG. 6(4), a given chip 105′ is placed in position of the substrate 102, followed by moving a heating head 106 from below and hot pressing the chip 105′ against the substrate 102 to move the thin chip 105′ on the substrate 102 as shown in FIG. 6(5), thereby bonding them together through an adhesive 103. The characteristic properties of each chip 105′ have been preliminarily measured prior to the division in the form of a wafer, thereby individually confirming non-defective and defective chips. Accordingly, non-defective chips alone are selectively placed in position, and are moved and bonded on the substrate 102.
[46] 46. It will be noted that in Examples 2 and 3, the tape 107 used is the same type as of that used in Example 1, and other types of tapes may also be used. EXAMPLE 4
[47] 47. This example illustrates bonding of a thin chip and a substrate by face-down-bonding wherein the main surface of the chip and the main surface of the substrate are facing each other.
[48] 48. Initially, as shown in FIG. 7(1), a Si wafer 105 is fixed on a first tape 107 attached to a first frame 101 by means of a pressure sensitive tape. Thereafter, as shown in FIG. 7(2), the Si wafer is thinned in the same manner as in Example 2.
[49] 49. Next, as shown in FIG. 7(3), the surface of the Si wafer 105 is turned down and is placed in face-to-face relation with the surface of a second tape 107′ attached to a second frame 101′, thereby sticking them together.
[50] 50. The first tape 107 is released from the Si wafer 105 to obtain such a structure that the Si wafer 105 is formed on the surface of the second tape 107′. Subsequently, as shown in FIG. 7(4), dicing grooves 104 are formed in the Si wafer 105 to divide the wafer into a plurality of chips 105′.
[51] 51. As shown in FIG. 7(5), a given chip 105′ is placed in position of the substrate 102, followed by moving a heating head 106 from below and hot-pressing to bond the thin chip 105′ on the substrate 102 through an anisotropic conductive adhesive 103 as shown in FIG. 7(6).
[52] 52. According to this example, the chip 105′ is moved on the substrate 102 after the movement on the second tape 107′. This changes up and bottom sides when compared with the case of Example 1. More particularly, the initial upper surface of Si wafer 105 is kept up after having been bonded to the substrate 102. Accordingly, in this example, if a desired semiconductor device is formed on the surface of the Si wafer 105 after the Si wafer 105 has been made thin, the semiconductor device is arranged on the surface of the chip 105′ which has been formed on the surface of the substrate 102.
[53] 53. As will be clear from the foregoing, the following effects and advantages can be expected according to the invention.
[54] 54. (1) A very thin semiconductor chip is bonded on a substrate by means of an adhesive, and a pad formed on the surface of the semiconductor chip and a substrate electrode formed on the surface of the substrate are mutually electrically connected through the conductive particles contained in the adhesive, thereby ensuring a reduced possibility of breakage due to the bending and high reliability on the electric connection.
[55] 55. (2) Since the semiconductor wafer is thinned by means of an etchant which moves along the main surface of the wafer at a high speed, a uniformly thin semiconductor can be readily obtained without involving any strain or defects therein.
[56] 56. (3) The release of a thin semiconductor chip from the tape and the bonding to a substrate are performed in the same step, so that the thin semiconductor chip can be bonded on the substrate without cracking.
[57] 57. (4) While a desired semiconductor chip is selectively heated and compressed, it is moved on the substrate, thereby ensuring mounting of the thin chip on the substrate very easily at low costs.
[58] 58. (5) Each semiconductor chip can be bonded on a substrate by means of an anisotropic conductive adhesive, so that the chip can be electrically connected with the substrate without wire bonding.
[59] 59. (6) The thickness of the semiconductor chip is so small as from 0.1 to 110 μm, within which the chip is able to bend, thus making it possible to realize a bend-resistance, thin semiconductor device.
权利要求:
Claims (11)
[1" id="US-20010000079-A1-CLM-00001] 1. A method for fabricating a semiconductor device, comprising the steps of:
providing a plurality of IC chips completely separated by dicing and attached to a dicing tape;
oppositely facing a substrate with a wiring to one IC chip of said plurality of IC chips, the one IC chip being attached to said dicing tape; and
fixing said IC chip to said substrate by selectively heating and press-contacting said IC chip facing to said substrate.
[2" id="US-20010000079-A1-CLM-00002] 2. A method for fabricating a semiconductor device according to
claim 1 , wherein said IC chip is fixed to said substrate with adhesive agent.
[3" id="US-20010000079-A1-CLM-00003] 3. A method for fabricating a semiconductor device according to
claim 2 , wherein said adhesive agent is an anisotropic electroconductive adhesive agent.
[4" id="US-20010000079-A1-CLM-00004] 4. A method for fabricating a semiconductor device according to
claim 1 , wherein the plurality of IC chips attached to the tape are from a wafer and are arranged as a wafer as attached to the tape.
[5" id="US-20010000079-A1-CLM-00005] 5. A method for fabricating a semiconductor device, comprising the steps of:
providing a plurality of IC chips completely separated and attached to a tape;
oppositely facing a substrate with a wiring to one IC chip of said plurality of IC chips; the one IC chip being attached to said tape; and
fixing said IC chip to said substrate by pushing out said IC chip opposing to said substrate by a heating head and press-contacting said IC chip with said substrate.
[6" id="US-20010000079-A1-CLM-00006] 6. A method for fabricating a semiconductor device according to
claim 5 , wherein said heating head has a flat surface.
[7" id="US-20010000079-A1-CLM-00007] 7. A method for fabricating a semiconductor device according to
claim 5 , wherein the plurality of IC chips attached to the tape are from a wafer and are arranged as a wafer as attached to the tape.
[8" id="US-20010000079-A1-CLM-00008] 8. A method for fabricating a semiconductor device, comprising the steps of:
providing a plurality of IC chips completely separated by dicing, attached to a dicing tape, and having a thickness ranging from 0.1 μm-110 μm;
oppositely facing a substrate with a wiring to one IC chip of said plurality of IC chips, the one IC chip being attached to said dicing tape; and
fixing said IC chip to said substrate by selectively heating and press-contacting said IC chip facing to said substrate.
[9" id="US-20010000079-A1-CLM-00009] 9. A method for fabricating a semiconductor device according to
claim 8 , wherein the plurality of IC chips attached to the tape are from a wafer and are arranged as a wafer as attached to the tape.
[10" id="US-20010000079-A1-CLM-00010] 10. A method for fabricating a semiconductor device, comprising the steps of:
providing a plurality of IC chips completely separated, attached to a tape, and having a thickness ranging from 0.1 μm-110 μm;
oppositely facing a substrate with a wiring to one IC chip of said plurality of IC chips; the one IC chip being attached to said tape; and
fixing said IC chip to said substrate by pushing out said IC chip opposing to said substrate by a heating head and press-contacting said IC chip with said substrate.
[11" id="US-20010000079-A1-CLM-00011] 11. A method for fabricating a semiconductor device according to
claim 10 , wherein the plurality of IC chips attached to the tape are from a wafer and are arranged as a wafer as attached to the tape.
类似技术:
公开号 | 公开日 | 专利标题
US6514796B2|2003-02-04|Method for mounting a thin semiconductor device
US6589855B2|2003-07-08|Methods of processing semiconductor wafer and producing IC card, and carrier
KR100609806B1|2006-08-08|Manufacturing method of semiconductor device
US7218003B2|2007-05-15|Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
JP4100936B2|2008-06-11|Manufacturing method of semiconductor device
JPH0997806A|1997-04-08|Semiconductor device, its manufacture and adhesive member for dicing
JP2007042996A|2007-02-15|Semiconductor-device manufacturing method, and semiconductor manufacturing apparatus
US20090251879A1|2009-10-08|Die thinning processes and structures
JPH1174230A|1999-03-16|Manufacture of thin-film semiconductor device
JP3719921B2|2005-11-24|Semiconductor device and manufacturing method thereof
TWI251924B|2006-03-21|A process applied to semiconductor
JP2006140303A|2006-06-01|Method for manufacturing semiconductor apparatus
JP4057875B2|2008-03-05|Manufacturing method of semiconductor device
JP3618268B2|2005-02-09|Manufacturing method of semiconductor device
JP3197884B2|2001-08-13|Implementation method
WO2021024768A1|2021-02-11|Method for provisionally bonding semiconductor substrate
US20110294262A1|2011-12-01|Semiconductor package process with improved die attach method for ultrathin chips
JPH09293905A|1997-11-11|Semiconductor device and manufacture thereof
JPH09330992A|1997-12-22|Semiconductor device mounting body and its manufacture
JP2755927B2|1998-05-25|Method for manufacturing semiconductor device
JP4045674B2|2008-02-13|IC chip connection method
Haberger et al.1995|Extreme thin integrated circuits
JP2005353883A|2005-12-22|Manufacturing method of semiconductor device
JP2000195829A|2000-07-14|Manufacture of semiconductor device and method for dicing
JP2002141439A|2002-05-17|Semiconductor device and manufacturing method thereof
同族专利:
公开号 | 公开日
AU5659896A|1996-11-29|
CA2221127A1|1996-11-21|
EP0828292A1|1998-03-11|
DE69636338D1|2006-08-24|
WO1996036992A1|1996-11-21|
EP0828292A4|2000-01-05|
JPH08316194A|1996-11-29|
DE69636338T2|2007-07-05|
CN1514479A|2004-07-21|
EP0828292B1|2006-07-12|
AU718934B2|2000-05-04|
US6589818B2|2003-07-08|
TW420867B|2001-02-01|
KR100606254B1|2006-12-07|
US6162701A|2000-12-19|
CN1188563A|1998-07-22|
CN100466224C|2009-03-04|
KR19990014853A|1999-02-25|
US5893746A|1999-04-13|
CN1098534C|2003-01-08|
JP3197788B2|2001-08-13|
US20030027376A1|2003-02-06|
US6514796B2|2003-02-04|
引用文献:
公开号 | 申请日 | 公开日 | 申请人 | 专利标题
US20030207497A1|2001-07-16|2003-11-06|Michel Koopmans|Method and system for attaching semiconductor components to a substrate using local radiation curing of dicing tape|
US20030207496A1|2001-08-21|2003-11-06|Oki Electric Industry Co., Ltd.|Semiconductor device and method for manufacturing the same|
US20050009298A1|2001-09-20|2005-01-13|Shuichi Suzuki|Method for manufacturing semiconductor device|
US20090023250A1|2007-07-20|2009-01-22|Infineon Technologies Ag|Apparatus and method for producing semiconductor modules|
US20130288407A1|2012-04-25|2013-10-31|Advanced Optoelectronic Technology, Inc.|Method for manufacturing led package|
US20140127880A1|2012-11-07|2014-05-08|Semiconductor Components Industries, Llc|Semiconductor die singulation method and apparatus|
US20140127885A1|2012-11-07|2014-05-08|Semiconductor Components Industries, Llc|Semiconductor die singulation method|
EP3177463A4|2014-08-05|2018-06-27|Uniqarta, Inc.|Setting up ultra-small or ultra-thin discrete components for easy assembly|
US10373869B2|2017-05-24|2019-08-06|Semiconductor Components Industries, Llc|Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus|US3915784A|1972-04-26|1975-10-28|Ibm|Method of semiconductor chip separation|
DE3336606A1|1983-10-07|1985-04-25|Siemens AG, 1000 Berlin und 8000 München|METHOD FOR PRODUCING MICROPACK|
JPH06105718B2|1984-06-05|1994-12-21|日本電気株式会社|Semiconductor device and manufacturing method thereof|
JPH0682718B2|1985-08-12|1994-10-19|日本電信電話株式会社|Electronic device testing apparatus and method of using the same|
JPS6237939U|1985-08-27|1987-03-06|||
US4729963A|1986-11-21|1988-03-08|Bell Communications Research, Inc.|Fabrication method for modified planar semiconductor structures|
JPH01225509A|1988-03-04|1989-09-08|Sumitomo Electric Ind Ltd|Dividing method for semiconductor base|
JPH0715087B2|1988-07-21|1995-02-22|リンテック株式会社|Adhesive tape and method of using the same|
US5071787A|1989-03-14|1991-12-10|Kabushiki Kaisha Toshiba|Semiconductor device utilizing a face-down bonding and a method for manufacturing the same|
JPH0774328B2|1989-09-05|1995-08-09|千住金属工業株式会社|Adhesive for temporary fixing of electronic parts|
JP2835145B2|1990-05-28|1998-12-14|株式会社東芝|Electronic equipment|
DE4032397A1|1990-10-12|1992-04-16|Bosch Gmbh Robert|METHOD FOR PRODUCING A HYBRID SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE PRODUCED BY THE METHOD|
JP3055193B2|1991-03-19|2000-06-26|セイコーエプソン株式会社|Circuit connection method and liquid crystal device manufacturing method|
US5279704A|1991-04-23|1994-01-18|Honda Giken Kogyo Kabushiki Kaisha|Method of fabricating semiconductor device|
US5143855A|1991-06-17|1992-09-01|Eastman Kodak Company|Method for making contact openings in color image sensor passivation layer|
JPH0521529A|1991-07-16|1993-01-29|Sony Corp|Bonding apparatus|
JPH05152303A|1991-11-26|1993-06-18|Matsushita Electric Ind Co Ltd|Semiconductor device with protruding electrode, protruding electrode forming method and the semiconductor device mounting body|
JPH06105728B2|1992-02-06|1994-12-21|カシオ計算機株式会社|Method of joining semiconductor devices|
JP2994510B2|1992-02-10|1999-12-27|ローム株式会社|Semiconductor device and manufacturing method thereof|
JPH05283480A|1992-04-02|1993-10-29|Toshiba Corp|Connecting method for electronic circuit component|
US5517752A|1992-05-13|1996-05-21|Fujitsu Limited|Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate|
JPH0669278A|1992-08-18|1994-03-11|Toshiba Corp|Connecting method for semiconductor element|
JPH06105728A|1992-09-22|1994-04-19|Hino Motors Ltd|Head test device of seat for vehicle|
US5268065A|1992-12-21|1993-12-07|Motorola, Inc.|Method for thinning a semiconductor wafer|
JPH06204267A|1993-01-08|1994-07-22|Nec Yamagata Ltd|Manufacture of semiconductor device|
JPH06244095A|1993-02-12|1994-09-02|Dainippon Screen Mfg Co Ltd|Substrate cooling device|
JPH06260531A|1993-03-04|1994-09-16|Hitachi Ltd|Tape carrier semiconductor device|
JPH06349892A|1993-06-10|1994-12-22|Matsushita Electric Ind Co Ltd|Manufacture of semiconductor device|
US5428190A|1993-07-02|1995-06-27|Sheldahl, Inc.|Rigid-flex board with anisotropic interconnect and method of manufacture|
US5656552A|1996-06-24|1997-08-12|Hudak; John James|Method of making a thin conformal high-yielding multi-chip module|
EP2849864B1|2012-05-17|2016-03-16|Dow Global Technologies LLC|Hydroclone with inlet flow shield|US6342434B1|1995-12-04|2002-01-29|Hitachi, Ltd.|Methods of processing semiconductor wafer, and producing IC card, and carrier|
US6448153B2|1996-10-29|2002-09-10|Tru-Si Technologies, Inc.|Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners|
US6498074B2|1996-10-29|2002-12-24|Tru-Si Technologies, Inc.|Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners|
US6882030B2|1996-10-29|2005-04-19|Tru-Si Technologies, Inc.|Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate|
EP0948808A4|1996-10-29|2000-05-10|Trusi Technologies Llc|Integrated circuits and methods for their fabrication|
DE19840226B4|1998-09-03|2006-02-23|Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.|Method of applying a circuit chip to a carrier|
JP3447602B2|1999-02-05|2003-09-16|シャープ株式会社|Method for manufacturing semiconductor device|
US6465809B1|1999-06-09|2002-10-15|Kabushiki Kaisha Toshiba|Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof|
US6333208B1|1999-07-13|2001-12-25|Li Chiung-Tung|Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding|
US6350664B1|1999-09-02|2002-02-26|Matsushita Electric Industrial Co., Ltd.|Semiconductor device and method of manufacturing the same|
JP4239352B2|2000-03-28|2009-03-18|株式会社日立製作所|Manufacturing method of electronic device|
US6432752B1|2000-08-17|2002-08-13|Micron Technology, Inc.|Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages|
US20020098620A1|2001-01-24|2002-07-25|Yi-Chuan Ding|Chip scale package and manufacturing method thereof|
US6717254B2|2001-02-22|2004-04-06|Tru-Si Technologies, Inc.|Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture|
KR100411256B1|2001-09-05|2003-12-18|삼성전기주식회사|A wafer lapping process and a method of processing a wafer backside using the same|
US6787916B2|2001-09-13|2004-09-07|Tru-Si Technologies, Inc.|Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity|
US7045890B2|2001-09-28|2006-05-16|Intel Corporation|Heat spreader and stiffener having a stiffener extension|
US7110356B2|2001-11-15|2006-09-19|Fujitsu Limited|Pre-provisioning a light path setup|
US6624048B1|2001-12-05|2003-09-23|Lsi Logic Corporation|Die attach back grinding|
JP4100936B2|2002-03-01|2008-06-11|Necエレクトロニクス株式会社|Manufacturing method of semiconductor device|
US7535100B2|2002-07-12|2009-05-19|The United States Of America As Represented By The Secretary Of The Navy|Wafer bonding of thinned electronic materials and circuits to high performance substrates|
US20050064679A1|2003-09-19|2005-03-24|Farnworth Warren M.|Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods|
US20050064683A1|2003-09-19|2005-03-24|Farnworth Warren M.|Method and apparatus for supporting wafers for die singulation and subsequent handling|
US7713841B2|2003-09-19|2010-05-11|Micron Technology, Inc.|Methods for thinning semiconductor substrates that employ support structures formed on the substrates|
JP4514490B2|2004-03-29|2010-07-28|日東電工株式会社|Semiconductor wafer fragmentation method|
TWI299555B|2006-04-28|2008-08-01|Taiwan Tft Lcd Ass|Semiconductor flip-chip package component and fabricating method|
JP4589265B2|2006-05-22|2010-12-01|パナソニック株式会社|Semiconductor bonding method|
JP4589266B2|2006-05-22|2010-12-01|パナソニック株式会社|Semiconductor ultrasonic bonding method|
CN101460962B|2006-06-02|2011-01-12|株式会社日立制作所|Method for manufacturing inlet for IC tag|
JP5323331B2|2007-08-24|2013-10-23|リンテック株式会社|Wafer processing sheet|
FR2943849B1|2009-03-31|2011-08-26|St Microelectronics Grenoble 2|METHOD FOR PRODUCING SEMICONDUCTOR HOUSINGS AND SEMICONDUCTOR HOUSING|
US20110019370A1|2009-07-27|2011-01-27|Gainteam Holdings Limited|Flexible circuit module|
US8906782B2|2011-11-07|2014-12-09|Infineon Technologies Ag|Method of separating semiconductor die using material modification|
US9704820B1|2016-02-26|2017-07-11|Taiwan Semiconductor Manufacturing Company Ltd.|Semiconductor manufacturing method and associated semiconductor manufacturing system|
CN106549115B|2016-10-27|2018-07-20|武汉华星光电技术有限公司|The stripping means of anisotropic conductive film and anisotropic conductive film|
CN111509107B|2020-04-24|2021-06-04|湘能华磊光电股份有限公司|Method for separating N parts of reverse films from LED wafer|
法律状态:
2006-07-28| FPAY| Fee payment|Year of fee payment: 4 |
2010-07-23| FPAY| Fee payment|Year of fee payment: 8 |
2014-09-12| REMI| Maintenance fee reminder mailed|
2015-02-04| LAPS| Lapse for failure to pay maintenance fees|
2015-03-02| STCH| Information on status: patent discontinuation|Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
2015-03-24| FP| Expired due to failure to pay maintenance fee|Effective date: 20150204 |
优先权:
申请号 | 申请日 | 专利标题
JP7-120236||1995-05-18||
JP12023695A|JP3197788B2|1995-05-18|1995-05-18|Method for manufacturing semiconductor device|
US08/952,344|US5893746A|1995-05-18|1996-05-14|Semiconductor device and method for making same|
US09/289,658|US6162701A|1995-05-18|1999-04-12|Semiconductor device and method for making same|
US09/729,191|US6514796B2|1995-05-18|2000-12-05|Method for mounting a thin semiconductor device|US09/729,191| US6514796B2|1995-05-18|2000-12-05|Method for mounting a thin semiconductor device|
US10/260,409| US6589818B2|1995-05-18|2002-10-01|Method for mounting a thin semiconductor device|
[返回顶部]